Hierarchical multipliers: A framework for high-speed multiple error detecting architectures-MedSci.cn - 梅斯（MedSci）

Hierarchical multipliers: A framework for high-speed multiple error detecting architectures

Valinataj, M; Jantsch, A

Valinataj, M (通讯作者)，Babol Noshirvani Univ Technol, Fac Elect & Comp Eng, Babol 4714871167, Iran.

MICROELECTRONICS JOURNAL, 2022; 125 ():

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