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Timing Macro Modeling for Efficient Hierarchical Timing Analysis

Jiang, IHR; Lee, PY

Jiang, IHR (reprint author), Natl Taiwan Univ, Dept Elect Engn, Taipei, Taiwan.; Jiang, IHR (reprint author), Natl Taiwan Univ, Grad Inst Elect Engn, Taipei, Taiwan.

2018 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2018; (): 714

Abstract

As designs continue to grow in size and complexity, EDA paradigm shifts from flat to hierarchical timing analysis. In this paper, we discuss timing ma......

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