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FPGA Implementation of an NCO Based CDR for the JUNO Front-End Electronics

Marini, F; Bellato, M; Bergnoli, A; Brugnera, R; dal Corso, F; Corti, D; Dong, J; Garfagnini, A; Giaz, A; Gong, G; Hu, J; Isocrate, R; Jiang, X; Lippi, I; von Sturm, K; Aiello, S; Andronico, G; Antonelli, V; Bandini, W; Basilico, D; Brigatti, A; Barresi, A; Budano, A; Bruno, R; Caccianiga, B; Cammi, A; Caruso, R; Chiesa, D; Clementi, C; Costa, S; Ding, X; Dusini, S; Fabbri, A; Fargetta, M; Ford, R; Formozov, A; Giammarchi, M; Grassi, M; Landini, C; Lombardi, P; Lombardo, C; Mantovani, F; Mari, SM; Martellini, C; Martini, A; Meroni, E; Mezzetto, M; Miramonti, L; Montini, P; Montuschi, M; Nastasi, M; Ortica, F; Paoloni, A; Parmeggiano, S; Pelliccia, N; Previtali, E; Ranucci, G; Riondino, D; Re, AC; Ricci, B; Romani, A; Saggese, P; Serafini, A; Sirignano, C; Sisti, M; Stanco, L; Strati, V; Torri, M; Tuve, C; Verde, G; Votano, L

Marini, F (corresponding author), Univ Padua, Dept Phys & Astron, I-35122 Padua, Italy.; Marini, F (corresponding author), Roma Tre Univ, Dept Math & Phys, I-00154 Rome, Italy.

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2021; 68 (8): 1952

Abstract

This article describes a design of an field-programmable gate array (FPGA) implementation of a clock and data recovery (CDR) system. The core will be ......

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