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Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications

Yan, AB; He, ZH; Zhou, J; Cui, J; Ni, TM; Huang, ZF; Wen, XQ; Girard, P

Ni, TM (corresponding author), Anhui Polytech Univ, Coll Elect Engn, Wuhu 241000, Peoples R China.

MICROELECTRONICS JOURNAL, 2021; 111 ():

Abstract

This paper presents a dual-modular-redundancy and dual-level error-interception based triple-node-upset (TNU) tolerant latch design (namely DDETT) for......

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