期刊： IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021; 29 (7)
In this brief, we propose a logarithmic converter for floating-point numbers based on the piecewise linear (PWL) approximation method. The proposed me......
期刊： IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021; 29 (6)
Reed-Solomon erasure codes (RS-ECs) are widely used in packet communication and storage systems to recover erasures. When the RS-EC decoder is impleme......
期刊： IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021; 29 (4)
First-in-first-out (FIFO) line buffers occupy considerable logic gates and consume significant power of the feature from accelerated segment test (FAS......
期刊： IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021; 29 (7)
This brief presents a three-stage comparator and its modified version to improve the speed and reduce the kickback noise. Compared to the traditional ......
期刊： IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021; 29 (7)
This article describes a gain-stabilized integration time generation technique suitable for the pipelined successive approximation register (SAR) anal......
期刊： IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021; 29 (7)
Nowadays, many data are multidimensional, which are called tensors. Tensor computations have been applied in different fields and various software lib......
期刊： IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021; 29 (7)
A fast and accurate statistical eye diagram estimation method for high-speed nonlinear links is proposed in this article. Probability density function......
期刊： IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021; 29 (7)
As device integration density increases exponentially as predicted by Moore's law, power consumption becomes a bottleneck for system scaling where lea......
期刊： IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021; 29 (9)
A novel single parity check-multiplicity assignment decoding algorithm based on voltage magnitude (VM_SPC-MA) is proposed, which is applied to the con......
期刊： IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021; 29 (7)
Modern integrated circuits (ICs) include thousands of on-chip instruments to ensure that specifications are met and maintained. Scalable and flexible ......
期刊： IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021; 29 (5)
Many convolutional neural network (CNN) accelerators are proposed to exploit the sparsity of the networks recently to enjoy the benefits of both compu......
期刊： IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021; 29 (9)
In network-on-chip (NoC) designs, the intellectual property (IP) mapping problem is a critical issue and is usually solved by heuristic searches. Howe......
期刊： IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021; 29 (8)
To minimize the area of analog-to-digital converters (ADCs) for multichannel applications and break the SNDR limitation caused by DAC-induced nonlinea......
期刊： IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021; 29 (5)
A single-channel reconfigurable successive approximation register (SAR) analog-to-digital converter (ADC) is presented, which features its speed expan......
期刊： IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021; 29 (7)
Physical layer signal processing algorithms in the wireless domain are seeing increased use of machine learning algorithms, especially Bayesian method......
